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I am a postdoctoral scholar at NC State, working on security of cloud and edge devices. Specific vulnerabilities include JTAG, side-channels, faults and reverse engineering.

Currently, I am actively working on secure virtualization on cloud FPGAs, SCA for Microsoft's SEAL homomorphic encryption library and application of machine learning in SCA. 

About Me

FPGA Implementations

Xilinx ISE

Lattice-based key exchange (Edge)

Power side-channel in Microsoft's SEAL (Cloud)

Fault attacks on Neural Networks (Cloud, Edge)

Xilinx Vivado and Vitis HLS

Optimization and ML Tools

I regularly use SAT, MILP and TSP solvers for optimization. For training ML models, I use TensorFlow. 

Side Channel and Fault Injection
GPU Implementations

AES

Differential Power Analysis

Differential Electro-Magnetic Analysis

AES: Coalescing unit timing vulnerabiilty

AES

Riscure's DPA

Riscure's DFA (Voltage, Clock, EM Glitches)

Smarcard

TPC Service
JTAG Vulnerability

iPhone

Reverse-engineering, cache timing side-channel, power side-channel

Fully connected neural networks

MNIST

MNIST, AlexNet, VGG-16

Convolutional neural networks

Design Automation Conference (2022)

Asia South Pacific Design Automation Conference (2018--Present)

European Test Symposium (2016--2018)

Reviewer Service

DAC, DATE, FPGA etc.

TCAD, TVLSI, Design & Test etc.

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